Method of manufacturing and assembling semiconductor chips with offset pads
US8394672B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Aug 14, 2010 |
| Grant date | Mar 12, 2013 |
| Priority date | — |
| Expiry date | Dec 20, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor chip device includes a first semiconductor chip adapted to be stacked with a second semiconductor chip wherein the second semiconductor chip includes a side and first and second conductor structures projecting from the side. The first semiconductor chip includes a first edge, a first conductor pad, a first conductor pillar positioned on but laterally offset from the first conductor pad toward the first edge and that has a first lateral dimension and is adapted to couple to one of the first and second conductor structures, a second conductor pad positioned nearer the first edge than the first conductor pad, and a second conductor pillar positioned on but laterally offset from the second conductor pad and that has a second lateral dimension larger than the first lateral dimension and is adapted to couple to the other of the first and second conductor structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.