Transistor layout for manufacturing process control
US8394681B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 5, 2010 |
| Grant date | Mar 12, 2013 |
| Priority date | — |
| Expiry date | Aug 11, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
Abstract
A symmetrical circuit is disclosed (FIG. 4). The circuit includes a first transistor (220) having a first channel in a substantial shape of a parallelogram (FIG. 5A) with acute angles. The first transistor has a first current path (506) oriented in a first crystal direction (520). A first control gate (362) overlies the first channel. A second transistor (222) is connected to the first transistor and has a second channel in the substantial shape of a parallelogram with acute angles. The second transistor has a second current path (502) oriented parallel to the first current path. A second control gate (360) overlies the second channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.