Structure and method for stress latching in non-planar semiconductor devices

US8394684B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Sivananda K. Kanakasabapathy · Niskayuna, US
• Hemanth Jagannathan · Niskayuna, US
• Sanjay C. Mehta · Niskayuna, US

Key dates

• Filing date: Jul 22, 2010
• Grant date: Mar 12, 2013
• Expiry date: May 9, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/01

Abstract

Techniques are discloses to apply an external stress onto the source/drain semiconductor fin sidewall areas and latch the same onto the semiconductor fin before releasing the sidewalls for subsequent salicidation and contact formation. In particular, the present disclosure provides methods in which selected portions of a semiconductor are subjected to an amorphizing ion implantation which disorients the crystal structure of the selected portions of the semiconductor fins, relative to portions of the semiconductor fin that is beneath a gate stack and encapsulated with various liners. At least one stress liner is formed and then stress memorization occurs by performing a stress latching annealing. During this anneal, recrystallization of the disoriented crystal structure occurs. The at least one stress liner is removed and thereafter merging of the semiconductor fins in the source/drain regions is performed.