Interconnects for stacked non-volatile memory device and method
US8399307B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 25, 2012 |
| Grant date | Mar 19, 2013 |
| Priority date | — |
| Expiry date | Jun 25, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B63/84
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a memory device includes providing a substrate having a surface region, defining a cell region and first and second peripheral regions, sequentially forming a first dielectric material, a first wiring structure for a first array of devices, and a second dielectric material over the surface region, forming an opening region in the first peripheral region, the opening region extending in a portion of at least the first and second dielectric materials to expose portions of the first wiring structure and the substrate, forming a second wiring material that is overlying the second dielectric material and fills the opening region to form a vertical interconnect structure in the first peripheral region, and forming a second wiring structure from the second wiring material for a second array of devices, the first and second wiring structures being separated from each other and electrically connected by the vertical interconnect structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.