Through substrate via semiconductor components
US8399936B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 28, 2010 |
| Grant date | Mar 19, 2013 |
| Priority date | — |
| Expiry date | Jul 21, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/01079
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A structure and method of forming through substrate vias in forming semiconductor components are described. In one embodiment, the invention describes a method of forming a through substrate via by partially filling an opening with a fill material, and forming a first insulating layer over the first fill material thereby forming a gap over the opening. The method further includes forming a second insulating layer to close the gap thereby forming an enclosed cavity within the opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.