Semiconductor wafer alignment markers, and associated systems and methods
US8400634B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 8, 2010 |
| Grant date | Mar 19, 2013 |
| Priority date | — |
| Expiry date | Jul 18, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor wafer alignment markers and associated systems and methods are disclosed. A wafer in accordance with a particular embodiment includes a wafer substrate having an alignment marker that includes a first structure and a second structure, each having a pitch, with first features and second features positioned within the pitch. The first features are positioned to generate first phase portions of an interference pattern, with at least one of the first features having a width different than another of the first features in the pitch, and with the second features positioned to generate second phase portions of the interference pattern, with the second phase portions having a second phase opposite the first phase, and with at least one of the second features having a width different than that of another of the second features in the pitch. The pitch for the first structure is different than the pitch for the second structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.