System and method for reducing pin-count of memory devices, and memory device testers for same
US8400844B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2011 |
| Grant date | Mar 19, 2013 |
| Priority date | — |
| Expiry date | Sep 21, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/2602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, memory devices and systems are disclosed. In one embodiment, a non-volatile memory device receives command signals through the same input/output terminals that receive address signals and write data signals and transmit read data signals. The input/output terminals are connected to a multiplexer, which is responsive to a received mode control signal to couple the input/output terminals to either a command bus or an input/output bus. A latch in the memory device latches the command signals when the mode control signal causes the input/output terminals to be coupled to the input/output bus. As a result, the command signals continue to be applied to the command bus. When the mode control signal causes the input/output terminals to be coupled to the input/output bus, write data signals are clocked into the memory device and read data signals are clocked out of the memory device responsive to a received clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.