Disabling electrical connections using pass-through 3D interconnects and associated systems and methods
US8404521B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 10, 2012 |
| Grant date | Mar 26, 2013 |
| Priority date | — |
| Expiry date | Aug 10, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/13034
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a backside, an interconnect extending through the first die to the backside, an integrated circuit electrically coupled to the interconnect, and a first electrostatic discharge (ESD) device electrically isolated from the interconnect. A second microelectronic die has a front side coupled to the backside of the first die, a metal contact at the front side electrically coupled to the interconnect, and a second ESD device electrically coupled to the metal contact. In another embodiment, the first die further includes a substrate carrying the integrated circuit and the first ESD device, and the interconnect is positioned in the substrate to disable an electrical connection between the first ESD device and the interconnect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.