Methods of forming a gate structure
US8404576B2 · kind B2 · utility
1Cited by
4References
3Claims
0Family size
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Key dates
| Filing date | Mar 22, 2011 |
| Grant date | Mar 26, 2013 |
| Priority date | — |
| Expiry date | Aug 11, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
Abstract
A gate structure includes an insulation layer on a substrate, a first conductive layer pattern on the insulation layer, a metal ohmic layer pattern on the first conductive layer pattern, a diffusion reduction layer pattern on the metal ohmic layer pattern an amorphous layer pattern on the diffusion reduction layer pattern, and a second conductive layer pattern on the amorphous layer pattern. The gate structure may have a low sheet resistance and desired thermal stability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.