Transistor structure with a sidewall-defined intrinsic base to extrinsic base link-up region and method of forming the structure

US8405186B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Renata Camillo-Castillo · South Burlington, US
• Mattias E. Dahlstrom · Mill Valley, US
• Peter B. Gray · Jericho, US
• David L. Harame · South Burlington, US
• Russell T. Herrin · South Burlington, US
• Alvin J. Joseph · Williston, US
• Andreas D. Stricker · South Burlington, US

Key dates

• Filing date: Jun 17, 2010
• Grant date: Mar 26, 2013
• Expiry date: Jan 28, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D10/891

Abstract

Disclosed are embodiments of an improved transistor structure (e.g., a bipolar transistor (BT) structure or heterojunction bipolar transistor (HBT) structure) and a method of forming the transistor structure. The structure embodiments can incorporate a dielectric layer sandwiched between an intrinsic base layer and a raised extrinsic base layer to reduce collector-base capacitance Ccb, a sidewall-defined conductive strap for an intrinsic base layer to extrinsic base layer link-up region to reduce base resistance Rb and a dielectric spacer between the extrinsic base layer and an emitter layer to reduce base-emitter Cbe capacitance. The method embodiments allow for self-aligning of the emitter to base regions and further allow the geometries of different features (e.g., the thickness of the dielectric layer, the width of the conductive strap, the width of the dielectric spacer and the width of the emitter layer) to be selectively adjusted in order to optimize transistor performance.