Integrated circuit packaging system with stacked configuration and method of manufacture thereof
US8405197B2 · kind B2 · utility
7Cited by
8References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 25, 2009 |
| Grant date | Mar 26, 2013 |
| Priority date | — |
| Expiry date | Apr 7, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacture of an integrated circuit packaging system includes: providing a first stack layer including a first device over a first substrate, the first device including a through silicon via; configuring a second stack layer over the first stack layer, the second stack layer including an analog device; configuring a third stack layer over the second stack layer; and encapsulating the integrated circuit packaging system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.