Stub minimization for wirebond assemblies without windows
US8405207B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 2012 |
| Grant date | Mar 26, 2013 |
| Priority date | — |
| Expiry date | Apr 5, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A microelectronic package can include a substrate and a microelectronic element having a rear face facing a first surface of the substrate, a front face, and a column of element contacts extending in a first direction. Edges of the microelectronic element can define an axial plane extending in the first direction and a third direction normal to the rear face. The package can include columns of terminals extending in the first direction at a second surface of the substrate. The terminals can include first terminals exposed in a central region of the second surface and configured to carry address information usable by circuitry within the package to determine an addressable memory location within the microelectronic element. The central region may have a width not more than three and one-half times a minimum pitch between any two adjacent columns of the terminals. The axial plane can intersect the central region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.