Method for producing a plurality of chips and a chip produced accordingly

US8405210B2 · kind B2 · utility

Assignee

• Robert Bosch GmbH · DE

Inventors

• Torsten Kramer · Wannweil, DE
• Matthias Boehringer · Reutlingen, DE
• Stefan Pinter · Reutlingen, DE
• Hubert Benzel · Neckartenzlingen, DE
• Matthias Illing · Tübingen, DE
• Frieder Haag · Wannweil, DE
• Simon Ambruster · Wannweil, DE

Key dates

• Filing date: Jul 24, 2008
• Grant date: Mar 26, 2013
• Expiry date: May 22, 2029

Classification

• Technology area (CPC B): Performing Operations; Transporting
• CPC primary: B81C2201/053
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

A production method for chips, in which as many method steps as possible are carried out in the wafer composite, that is, in parallel for a plurality of chips disposed on a wafer. This is a method for producing a plurality of chips whose functionality is implemented on the basis of the surface layer of a substrate. In this method, the surface layer is patterned and at least one cavity is produced below the surface layer, so that the individual chip regions are connected to each other and/or to the rest of the substrate by suspension webs only, and/or so that the individual chip regions are connected to the substrate layer below the cavity via supporting elements in the region of the cavity. The suspension webs and/or supporting elements are cut when the chips are separated. The patterned and undercut surface layer of the substrate is embedded in a plastic mass before the chips are separated.