Hierarchical DRAM sensing
US8406073B1 · kind B1 · utility
4Cited by
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19Claims
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Key dates
| Filing date | Dec 22, 2010 |
| Grant date | Mar 26, 2013 |
| Priority date | — |
| Expiry date | May 2, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4094
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hierarchical DRAM sensing apparatus and method which employs local bit line pairs and global bit lines. A word line selects the cells in a cluster of sense amplifiers, each of the amplifiers being associated with a pair of bit lines. One of the local bit lines is selected for coupling to global bit lines and a global sense amplifier. Clusters are located in a plurality of subarrays forming a bank with the global bit lines extending from each of the banks to the global sense amplifier.
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