Glitch power reduction

US8407654B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Thomas Buechner · Rabenau, DE
• Markus Buehler · Holzgerlingen, DE
• Markus Olbrich · Langenhagen, DE
• Philipp Panitz · Eppelheim, DE
• Lei Wang · Hangzhou City, CN

Key dates

• Filing date: Feb 3, 2012
• Grant date: Mar 26, 2013
• Expiry date: Feb 3, 2032

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2119/06
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A method comprises reducing power consumption of an electronic circuit, wherein the electronic circuit comprises at least one logic cone with at least one gate having a single output net, wherein representations of the at least one gate are instances of elements from a standard cell library. Reducing of the power consumption comprises determining an upper bound for dynamic power consumption by calculating transition metrics and power metrics for each gate. Reducing of the power consumption comprises selecting gates with an upper bound for power consumption greater than a predetermined threshold value. For each selected gate, performing operations comprising: testing multiple configurations from the standard cell library for the selected gate by calculating respective upper bound for power consumption for each of the multiple configurations; selecting gate configuration with minimum upper bound for power consumption; and modifying the gate-level design representation according to the selected gate configuration.