Gate trim process using either wet etch or dry etch approach to target CD for selected transistors
US8409994B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 21, 2011 |
| Grant date | Apr 2, 2013 |
| Priority date | — |
| Expiry date | Oct 21, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed are methods and devices for targeting CD of selected transistors in a semiconductor device. Varying CD is done by forming hard mask lines in a hard mask layer that have varying amounts of spacer material associated therewith. Hard mask lines corresponding to selected transistors are either left covered or uncovered by a resist applied over the hard mask layer. Then, spacer material is selectively removed from the hard mask lines to vary the width of hard mask lines and associated side wall spacers. A gate layer is then etched through the spaces in the hard mask lines to form gate lines having varying widths and targeted CD.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.