CMOSFET device with controlled threshold voltage and method of fabricating the same
US8410555B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 24, 2010 |
| Grant date | Apr 2, 2013 |
| Priority date | — |
| Expiry date | May 6, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/601
Abstract
There is provided a CMOSFET device with a threshold voltage controlled by means of its gate stack configuration and a method of fabricating the same. The CMOSFET device comprises: a semiconductor substrate; am interface layer grown on the silicon substrate; a first high-k gate dielectric layer deposited on the interface layer; a very thin metal layer deposited on the first high-k gate dielectric layer; a second high-k gate dielectric layer deposited on the very thin metal layer; and a gate electrode layer deposited on the second high-k gate dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.