Three-dimensional stacked semiconductor integrated circuit
US8411478B2 · kind B2 · utility
3Cited by
0References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2010 |
| Grant date | Apr 2, 2013 |
| Priority date | — |
| Expiry date | May 25, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various embodiments of a three-dimensional, stacked semiconductor integrated circuit are disclosed. In one exemplary embodiment, the circuit may include a master slice, a plurality of slave slices, and a plurality of through-silicon vias for connecting the master slice to the plurality of slave slices. At least one of the plurality of through-silicon vias may be configured to transmit an operation control signal from the master slice to the plurality of slave slices. The at least one of the plurality of through-silicon vias is configured to be shared by the plurality of slave slices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.