Method and apparatus for cache control
US8412971B2 · kind B2 · utility
12Cited by
12References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 11, 2010 |
| Grant date | Apr 2, 2013 |
| Priority date | — |
| Expiry date | Nov 18, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for dynamically controlling a cache size is disclosed. In one embodiment, a method includes changing an operating point of a processor from a first operating point to a second operating point, and selectively removing power from one or more ways of a cache memory responsive to changing the operating point. The method further includes processing one or more instructions in the processor subsequent to removing power from the one or more ways of the cache memory, wherein said processing includes accessing one or more ways of the cache memory from which power was not removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.