Memory device and method of fabricating the same
US8415728B2 · kind B2 · utility
3Cited by
5References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2010 |
| Grant date | Apr 9, 2013 |
| Priority date | — |
| Expiry date | May 10, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/488
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory device includes a mesa structure and a word line. The mesa structure, having two opposite side surfaces, includes at least one pair of source/drain regions and at least one channel base region corresponding to the pair of source/drain regions formed therein. The word line includes two linear sections and at least one interconnecting portion. Each linear section extends on the respective side surface of the mesa structure, adjacent to the channel base region. The at least one interconnecting portion penetrates through the mesa structure, connecting the two linear sections.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.