ETSOI CMOS with back gates
US8415743B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 2011 |
| Grant date | Apr 9, 2013 |
| Priority date | — |
| Expiry date | Sep 28, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
Abstract
A structure has a functional region having a first type of conductivity and a top surface. The functional region is connected to a bias contact. The structure further includes an insulating layer; a semiconductor layer and first and second transistor devices having the same type of conductivity disposed upon the semiconductor layer. The structure further includes a first back gate region adjacent to the top surface and underlying one of the transistor devices, the first back gate region having a second type of conductivity; and a second back gate region adjacent to the top surface and underlying the other one of the transistor devices, the second back gate region having the first type of conductivity. The first transistor device has a first characteristic threshold voltage and the second transistor device has a second characteristic threshold voltage that differs from the first characteristic threshold voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.