Patent · US Active

Lead frame for semiconductor package

US8415779B2 · kind B2 · utility

2Cited by

6References

18Claims

0Family size

Assignee

Freeescale Semiconductor, Inc. · US

Inventors

Tzu Ling Wong · Kuala Lumpur, MY
Chee Seng Foong · Bandar Baru Sungai Buloh, MY
Kai Yun Yow · Petaling Jaya, MY

Key dates

Filing date	Mar 15, 2011
Grant date	Apr 9, 2013
Priority date	—
Expiry date	Aug 25, 2031

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/181
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A lead frame for providing electrical interconnection to an Integrated Circuit (IC) die. The lead frame includes a die support area for receiving and supporting the IC die and a plurality of leads surrounding the die support area. A plurality of interconnect receiving portions is formed in the die support area. The interconnect receiving portions are for providing electrical interconnection to first bumps on a bottom surface of the IC die. The leads are for providing electrical interconnection to second bumps on a surface of the IC die, the second bumps surrounding the first bumps.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.