Apparatus and methodology for testing stacked die
US8415783B1 · kind B1 · utility
24Cited by
15References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 4, 2007 |
| Grant date | Apr 9, 2013 |
| Priority date | — |
| Expiry date | May 6, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A packaged integrated circuit (“IC”) has a daughter IC die stacked on a backside of a parent IC die. Backside fill material is applied to the backside of the parent IC die to provide a planarized surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.