Thermally enhanced semiconductor package system
US8415786B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 3, 2012 |
| Grant date | Apr 9, 2013 |
| Priority date | — |
| Expiry date | Apr 3, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3656
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package system is provided including: a semiconductor chip; a substrate having a substrate opening and a vertical build-up wing, the substrate having the semiconductor chip mounted thereon with the vertical build-up wing circumscribed by vertical planes of a perimeter of, and spaced apart from, the semiconductor chip; a first heat slug attached above the substrate at a first horizontal plane and to a first surface of the semiconductor chip, the semiconductor chip at least partially encapsulated by the first heat slug; and a second heat slug attached to the substrate at a second horizontal plane above the first horizontal plane and to a second surface of the semiconductor chip through the substrate opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.