Semiconductor device with die stack arrangement including staggered die and efficient wire bonding
US8415808B2 · kind B2 · utility
16Cited by
4References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2010 |
| Grant date | Apr 9, 2013 |
| Priority date | — |
| Expiry date | Dec 24, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor die package is disclosed. An example of the semiconductor package includes a first group of semiconductor die interspersed with a second group of semiconductor die. The die from the first and second groups are offset from each other along a first axis and staggered with respect to each other along a second axis orthogonal to the first axis. A second example of the semiconductor package includes an irregular shaped edge and a wire bond to the substrate from a semiconductor die above the lowermost semiconductor die in the package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.