Erase and programming techniques to reduce the widening of state distributions in non-volatile memories
US8416624B2 · kind B2 · utility
19Cited by
71References
40Claims
0Family size
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Key dates
| Filing date | Mar 25, 2011 |
| Grant date | Apr 9, 2013 |
| Priority date | — |
| Expiry date | Oct 12, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3404
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are presented for use in memory devices to improve reliability and endurance by reducing the widening in state distributions, that occurs after multiple write/erase cycles. One set of techniques uses a pre-conditioning operation where a pulse series, which may include program and gentle erase, are applied to one or more wordlines while a voltage differential is applied in the wordline direction, bitline direction, or both. Another set of techniques uses a dual or multi-pulse program process, where an increased wordline-to-wordline differential used in the first pulse of a pair.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.