Techniques for controlling a semiconductor memory device
US8416636B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2010 |
| Grant date | Apr 9, 2013 |
| Priority date | — |
| Expiry date | Jul 11, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for controlling a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for controlling a semiconductor memory device including applying a plurality of voltage potentials to a plurality of memory cells arranged in an array of rows and columns. Applying the plurality of voltage potentials to the plurality of memory cells may include applying a first voltage potential to a first memory cell in a row of the array via a first respective bit line and a first switch transistor, applying a second voltage potential to a second memory cell in the row of the array via a second respective bit line and a second switch transistor, and applying a third voltage potential to at least one third memory cell in the row of the array via at least one third respective bit line and at least one third switch transistor, wherein the at least one third memory cell may be located between the first memory cell and the second memory cell in the row of the array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.