Compilation and simulation of a circuit design
US8418095B1 · kind B1 · utility
5Cited by
1References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 10, 2012 |
| Grant date | Apr 9, 2013 |
| Priority date | — |
| Expiry date | May 10, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/331
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One or more embodiments provide a method of HDL simulation that determines characteristics of nets, such as shorting of nets, non-blocking assignments, etc., for the entire circuit design during compilation. Simulation code and data structures are generated for each net, individually, based on the determined characteristics of the respective net. As a result, rather than implementing code for simulation of each net capable of handling every possible combination of the characteristics, less complex code and data structures may be generated for simulation of the nets.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.