Methods for pattern matching in a double patterning technology-compliant physical design flow
US8418105B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 12, 2012 |
| Grant date | Apr 9, 2013 |
| Priority date | — |
| Expiry date | Jan 12, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for fabricating an integrated circuit is disclosed that includes, in accordance with an embodiment, providing a drawn layout logical design for the integrated circuit, the logical design including a plurality of patterns; checking the plurality of patterns for double patterning technology compliance; identifying a non-double patterning technology compliant pattern; providing a double patterning technology compliant pattern for replacing the identified non-double patterning technology compliant pattern, thereby creating a modified logical design; generating a mask set implementing the modified logical design; and employing the mask set to implement the modified logical design in and on a semiconductor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.