Techniques for employing retiming and transient simplification on netlists that include memory arrays
US8418106B2 · kind B2 · utility
1Cited by
21References
14Claims
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Key dates
| Filing date | Aug 31, 2010 |
| Grant date | Apr 9, 2013 |
| Priority date | — |
| Expiry date | Jan 2, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique for performing an analysis of a logic design (that includes a native memory array embodied in a netlist) includes detecting an initial transient behavior in the logic design as embodied in the netlist. The technique also includes determining a duration of the initial transient behavior and gathering reduction information on the logic design based on the initial transient behavior. The netlist is then modified based on the reduction information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.