Zone-based optimization framework for performing timing and design rule optimization
US8418116B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2010 |
| Grant date | Apr 9, 2013 |
| Priority date | — |
| Expiry date | Nov 4, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Some embodiments of the present invention provide techniques and systems for efficiently optimizing a circuit design for one or more multi-mode multi-corner (MCMM) scenarios. A system can select an optimizing transformation for a logic gate, which if applied to the logic gate, does not degrade a timing metric in a local context of the logic gate. Next, the system can determine whether applying the optimizing transformation to the logic gate degrades the timing metric in a zone around the logic gate. If so, the system can reject the optimizing transformation. Otherwise, the system can determine whether applying the optimizing transformation to the logic gate degrades the timing metric in the circuit design. If so, the system can reject the optimizing transformation. Otherwise, the system can accept the optimizing transformation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.