Logical circuit netlist reduction and model simplification using simulation results containing symbolic values
US8418119B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 10, 2011 |
| Grant date | Apr 9, 2013 |
| Priority date | — |
| Expiry date | May 10, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A logic synthesis program, method and system for simplifying and/or reducing a logic design receives output from a logic simulator that uses symbolic values for stimulus and contains symbolic values in the logic simulator output. Relationships between the nodes dependent on symbolic values can be used to merge nodes or otherwise simplify the logic design. Behaviors such as oscillators, transient values, identical signals, dependent logical states and chicken-switch determined states that depend on the symbolic values can be detected in the simulation results and the netlist simplified using the results of the detection. The netlist can be simplified by inserting registers to represent nodes that assume a symbolic value or combination based on symbolic values either statically or after an initial transient. Oscillating nodes can be replaced with equivalent oscillator circuits, and nodes having values dependent on chicken-switch operation can be detected and replaced with registers initialized from the chicken-switch input states.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.