Method for integration of interpretation and translation in a microprocessor
US8418153B2 · kind B2 · utility
0Cited by
60References
21Claims
0Family size
Inventors
Key dates
| Filing date | Oct 13, 2009 |
| Grant date | Apr 9, 2013 |
| Priority date | — |
| Expiry date | Nov 6, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/45516
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for executing a target application on a host processor including the steps of translating each target instruction being to be executed into host instructions, storing the translated host instructions, executing the translated host instructions, responding to an exception during execution of a translated instruction by rolling back to a point in execution at which correct state of a target processor is known, and interpreting each target instruction in order from the point in execution at which correct state of a target processor is known.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.