Replacement gate devices with barrier metal for simultaneous processing

US8420473B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Takashi Ando · Tuckahoe, US
• Michael P. Chudzik · Beacon, US
• Siddarth A. Krishnan · Newark, US
• Unoh Kwon · Fishkill, US
• Vijay Narayanan · New York, US

Key dates

• Filing date: Dec 6, 2010
• Grant date: Apr 16, 2013
• Expiry date: Sep 15, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/68

Abstract

A method of simultaneously fabricating n-type and p type field effect transistors can include forming a first replacement gate having a first gate metal layer adjacent a gate dielectric layer in a first opening in a dielectric region overlying a first active semiconductor region. A second replacement gate including a second gate metal layer can be formed adjacent a gate dielectric layer in a second opening in a dielectric region overlying a second active semiconductor region. At least portions of the first and second gate metal layers can be stacked in a direction of their thicknesses and separated from each other by at least a barrier metal layer. The NFET resulting from the method can include the first active semiconductor region, the source/drain regions therein and the first replacement gate, and the PFET resulting from the method can include the second active semiconductor region, source/drain regions therein and the second replacement gate.