Patent · US Active

Methods for fabricating integrated circuits with controlled P-channel threshold voltage

US8420519B1 · kind B1 · utility

3Cited by

6References

19Claims

0Family size

Assignee

GlobalFoundries Inc. · KY

Inventors

Dina H. Triyoso · Mechanicville, US
Elke Erben · Dresden, DE
Klaus Hempel · Dresden, DE

Key dates

Filing date	Nov 1, 2011
Grant date	Apr 16, 2013
Priority date	—
Expiry date	Nov 1, 2031

Classification

Technology area (CPC H)Electricity
CPC primaryH10D64/691
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Methods are provided for fabricating integrated circuits having controlled threshold voltages. In accordance with one embodiment a method includes forming a gate dielectric overlying an N-doped silicon substrate and depositing a layer of titanium nitride and a layer of tantalum nitride overlying the gate dielectric. A sub-monolayer of tantalum oxide is deposited overlying the layer of tantalum nitride by a process of atomic layer deposition, and oxygen is diffused from the tantalum oxide through the tantalum nitride and titanium nitride.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.