Test structures for through silicon vias (TSVs) of three dimensional integrated circuit (3DIC)
US8421073B2 · kind B2 · utility
8Cited by
0References
20Claims
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Key dates
| Filing date | Jan 14, 2011 |
| Grant date | Apr 16, 2013 |
| Priority date | — |
| Expiry date | Oct 23, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A plurality of through silicon vias (TSVs) on a substrate or in a 3 dimensional integrated circuit (3DIC) are chained together. TSVs are chained together to increase the electrical signal. A plurality of test pads are used to enable the testing of the TVSs. One of the test pads is grounded. The remaining test pads are either electrically connected to TSVs in the chain or grounded.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.