Defect and critical dimension analysis systems and methods for a semiconductor lithographic process
US8422761B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2009 |
| Grant date | Apr 16, 2013 |
| Priority date | — |
| Expiry date | Jun 4, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2207/30148
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus and method evaluate a wafer fabrication process for forming patterns on a wafer based upon design data. Within a recipe database, two or more inspection regions are defined on the wafer for analysis. Patterns within each of the inspection regions are automatically selected based upon tendency for measurement variation resulting from variation in the fabrication process. For each inspection region, at least one image of patterns within the inspection region is captured, a reference pattern, represented by one or both of (a) one or more line segments and (b) one or more curves, is automatically generated from the design data. An inspection unit detects edges within each of the images and registers the image with the reference pattern. One or more measurements are determined from the edges for each of the selected patterns and are processed within a statistical analyzer to form statistical information associated with the fabrication process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.