Stress memorization with reduced fringing capacitance based on silicon nitride in MOS semiconductor devices

US8426266B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Jan Hoentschel · Dresden, DE
• Andreas Kurz · Oberursel, DE
• Uwe Griebenow · Markkleeberg, DE
• Thilo Scheiper · Dresden, DE

Key dates

• Filing date: Dec 9, 2010
• Grant date: Apr 23, 2013
• Expiry date: Jun 24, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/0227
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

In sophisticated semiconductor devices, stress memorization techniques may be applied on the basis of a silicon nitride material, which may be subsequently modified into a low-k dielectric material in order to obtain low-k spacer elements, thereby enhancing performance of sophisticated semiconductor devices. The modification of the initial silicon nitride-based spacer material may be accomplished on the basis of an oxygen implantation process.