Method of fabricating a double-gate transistor and a tri-gate transistor on a common substrate
US8426283B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 10, 2011 |
| Grant date | Apr 23, 2013 |
| Priority date | — |
| Expiry date | Nov 18, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0158
Abstract
A method of fabricating a double-gate transistor and a tri-gate transistor on a common substrate, in which, a substrate includes a first fin structure covered with a first mask layer and a second fin structure covered with a second mask layer, the first mask layer is removed, a gate material layer is formed and covers the first fin structure and the second mask layer, the gate material layer is patterned to result in a tri-gate structure covering the first fin structure and a double-gate structure covering the second fin structure and the second mask layer, and a source and a drain are formed in each of these two fin structures each at two sides of the gates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.