3D memory array arranged for FN tunneling program and erase
US8426294B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 2012 |
| Grant date | Apr 23, 2013 |
| Priority date | — |
| Expiry date | May 21, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A 3D memory device includes an array of semiconductor body pillars and bit line pillars, dielectric charge trapping structures, and a plurality of levels of word line structures arranged orthogonally to the array of semiconductor body pillars and bit line pillars. The semiconductor body pillars have corresponding bit line pillars on opposing first and second sides, providing source and drain terminals. The semiconductor body pillars have first and second channel surfaces on opposing third and fourth sides. Dielectric charge trapping structures overlie the first and second channel surfaces, providing data storage sites on two sides of each semiconductor body pillar in each level of the 3D array. The device can be operated as a 3D AND-decoded flash memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.