Self-aligned contact for replacement gate devices
US8426300B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 2, 2010 |
| Grant date | Apr 23, 2013 |
| Priority date | — |
| Expiry date | Sep 7, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A conductive top surface of a replacement gate stack is recessed relative to a top surface of a planarization dielectric layer by at least one etch. A dielectric capping layer is deposited over the planarization dielectric layer and the top surface of the replacement gate stack so that the top surface of a portion of the dielectric capping layer over the replacement gate stack is vertically recessed relative to another portion of the dielectric layer above the planarization dielectric layer. The vertical offset of the dielectric capping layer can be employed in conjunction with selective via etch processes to form a self-aligned contact structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.