Memory device and method of fabricating the same
US8426925B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2010 |
| Grant date | Apr 23, 2013 |
| Priority date | — |
| Expiry date | Apr 25, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/488
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory device includes a plurality of isolations and trench fillers arranged in an alternating manner in a direction, a plurality of mesa structures between the isolations and trench fillers, and a plurality of word lines each overlying a side surface of the respective mesa. In one embodiment of the present invention, the width measured in the direction of the trench filler is smaller than that of the isolation, each mesa structure includes at least one paired source/drain regions and at least one channel base region corresponding to the paired source/drain regions, and each of the word lines is on a side surface of the mesa structure, adjacent the respective isolation, and is arranged adjacent the channel base region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.