Mixed-mode input buffer
US8427204B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 2, 2010 |
| Grant date | Apr 23, 2013 |
| Priority date | — |
| Expiry date | Jul 2, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00361
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An input buffer with a reduced sensitivity to an externally generated reference voltage includes: a first input coupled between a first load and ground, the first input being an externally generated reference voltage; a second input coupled between a second load and ground, for generating an output; and a third input coupled in parallel to the first input, the third input being an internally generated reference voltage. The output switches between high and low or vice versa when the second input exceeds a switching point which is an average of the first input and the third input according to the relative size of the first input and the third input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.