Methods and system for analysis and management of parametric yield
US8429576B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2012 |
| Grant date | Apr 23, 2013 |
| Priority date | — |
| Expiry date | May 15, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.