Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US8431469B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 7, 2011 |
| Grant date | Apr 30, 2013 |
| Priority date | — |
| Expiry date | Feb 7, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electrical device in which an interface layer is disposed between and in contact with a metal and a Si-based semiconductor, the interface layer being of a thickness effective to depin of the Fermi level of the semiconductor while still permitting current to flow between the metal and the semiconductor. The interface layer may include a layer of a passivating material (e.g., made from nitrogen, oxygen, oxynitride, arsenic, hydrogen and/or fluorine) and sometimes also includes a separation layer. In some cases, the interface layer may be a monolayer of a semiconductor passivating material. The interface layer thickness corresponds to a minimum specific contact resistance of less than or equal to 10 Ω-μm2 or even less than or equal to 1 Ω-μm2 for the electrical device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.