Patent · US Active

Detection of word-line leakage in memory arrays

US8432732B2 · kind B2 · utility

39Cited by

70References

7Claims

0Family size

Assignee

Sandisk Technologies, Inc. · US

Inventors

Yan Li · Milpitas, US
Dana Lee · Saratoga, US
Jonathan Huynh · San Jose, US

Key dates

Filing date	Jul 9, 2010
Grant date	Apr 30, 2013
Priority date	—
Expiry date	Jun 21, 2031

Classification

Technology area (CPC G)Physics
CPC primaryG11C2029/5006
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Techniques and corresponding circuitry are presented for the detection of wordline leakage in a memory array. In an exemplary embodiment, a capacitive voltage divider is used to translate the high voltage drop to low voltage drop that can be compared with a reference voltage to determine the voltage drop due to leakage. An on-chip self calibration method can help assure the accuracy of this technique for detecting leakage limit.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.