Patent · US Active

Prefetching of next physically sequential cache line after cache line that includes loaded page table entry

US8433853B2 · kind B2 · utility

4Cited by

7References

20Claims

0Family size

Assignee

VIA Technologies, Inc. · TW

Inventors

Colin Eddy · Austin, US
Rodney E. Hooker · Austin, US

Key dates

Filing date	Mar 6, 2012
Grant date	Apr 30, 2013
Priority date	—
Expiry date	Mar 6, 2032

Classification

Technology area (CPC G)Physics
CPC primaryG06F2212/6028
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A microprocessor includes a translation lookaside buffer, a request to load a page table entry into the microprocessor generated in response to a miss of a virtual address in the translation lookaside buffer, and a prefetch unit. The prefetch unit receives a physical address of a first cache line that includes the requested page table entry and responsively generates a request to prefetch into the microprocessor a second cache line that is the next physically sequential cache line to the first cache line.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.