Vertical mirror in a silicon photonic circuit

US8435809B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• John Heck · Berkeley, US
• Ansheng Liu · Cupertino, US
• Michael T. Morse · San Jose, US
• Haisheng Rong · Pleasanton, US

Key dates

• Filing date: Sep 25, 2009
• Grant date: May 7, 2013
• Expiry date: Jul 28, 2031

Classification

• Technology area (CPC G): Physics
• CPC primary: G02B6/4214
• WIPO field: Optics
• WIPO sector: Instruments

Abstract

A vertical total internal reflection (TIR) mirror and fabrication thereof is made by creating a re-entrant profile using crystallographic silicon etching. Starting with an SOI wafer, a deep silicon etch is used to expose the buried oxide layer, which is then wet-etched (in HF), opening the bottom surface of the Si device layer. This bottom silicon surface is then exposed so that in a crystallographic etch, the resulting shape is a re-entrant trapezoid with facets These facets can be used in conjunction with planar silicon waveguides to reflect the light upwards based on the TIR principle. Alternately, light can be coupled into the silicon waveguides from above the wafer for such purposes as wafer level testing.