Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods
US8435836B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 14, 2011 |
| Grant date | May 7, 2013 |
| Priority date | — |
| Expiry date | Jan 14, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods are disclosed. A system in accordance with a particular embodiment includes a first semiconductor substrate having a first substrate material, and a penetrating structure carried by the first semiconductor substrate. The system further includes a second semiconductor substrate having a second substrate material with a preformed recess. The penetrating structure of the first semiconductor substrate is received in the recess of the second semiconductor substrate and is mechanically engaged with the recess and secured to the second semiconductor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.