Implementing semiconductor SoC with metal via gate node high performance stacked transistors

US8435851B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Karl R. Erickson · Rochester, US
• Phil C. Paone · Rochester, US
• David P. Paulsen · Dodge Center, US
• John E. Sheets, II · Zumbrota, US
• Gregory J. Uhlmann · Rochester, US
• Kelly L. Williams · Rochester, US

Key dates

• Filing date: Jan 12, 2011
• Grant date: May 7, 2013
• Expiry date: Apr 13, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

A method and structures are provided for implementing metal via gate node high performance stacked vertical transistors in a back end of line (BEOL) on a semiconductor System on Chip (SoC). The high performance stacked vertical transistors include a pair of stacked vertical field effect transistors (FETs) formed by polycrystalline depositions in a stack between planes of a respective global signal routing wire. A channel length of each of the stacked vertical FETs is delineated by the polycrystalline depositions with sequential source deposition, channel deposition and drain deposition; and a wire via defines the gate node.